1. Field of the Invention
The present invention relates generally to programmable logic devices (PLDs). More particularly, the invention relates to memory initialization of PLDs.
2. Description of the Related Art
Programmable logic devices (PLDs) generally include an array of uncommitted elements that can be interconnected in a general way. PLDs provide storage, logic and wires in a standard package that can be programmed by the user according to the specification of the user to make an application specific integrated circuit (ASIC). When first introduced, PLDs had simple designs and were costly, therefore, they were primarily used in prototypes, and emulation systems. Currently, PLDs are relatively inexpensive and include all the features needed to implement most complex hardware designs. As a result, they are used in preproduction applications as well as in marketed products.
With the constant drive to reduce the size of electronic products and their components, it would be beneficial that PLDs be laid out in an efficient manner. That is, in order to reduce the area required by a PLD, the resources of the PLD need to be allocated efficiently so that unwanted additional elements can be avoided to save the real estate required by the PLDs. At the same time the improved layout should not diminish the speed characteristics for the PLD.
The embedded memory block of a PLD typically supports using an initialization file to pre-load the PLD configuration into memory. The addresses used for pre-loading the initialization file are decoded addresses. These addresses are multiplexed and then buffered in order to drive the memory block wordlines, as the multiplexers are incapable of handling the heavy loading required by the memory array in the memory block. This additional circuitry can not only occupy valuable real-estate space, but also affect the speed of the device.
Accordingly, there exists a need for a system and a method for revising the architecture supporting memory pre-loading in a PLD.